A typical 2-transistor (2T) EEPROM, as shown in FIG. 1, consists of one floating-gate n-channel memory cell (e.g. FLOTOX or flash types) as well as one n-channel MOS transistor as the access switch. The FLOTOX cell has a small window (not shown in FIG. 1) with a thin tunnel oxide formed between the drain and the floating-gate to allow electrons to tunnel through when a sufficient electrical field is applied. The flash cell in FIG. 1 is a simple stack floating-gate transistor with a thin tunnel oxide between the floating-gate and the channel of the cell. The floating gate can be negatively charged (i.e. programmed) or discharged (i.e. erased) by allowing electrons to move through the thin tunnel oxide (.about.80 A to 110 A) under a high electric field (.about.10MV/cm) through a process known as Fowler-Nordheim (F-N) tunneling mechanism. The access transistor switch is used for isolating the memory cell from column circuits and it facilitates the program and erase operations of one single cell. In contrast, flash memory (without the access transistor for each cell) can only be erased in blocks. Certainly the 2T EEPROM cell is large in size compared with the 1T flash cell, although it has full non-volatile functions.
There are drawbacks to both the 2T EEPROM cell or the 1T flash cell. First, the F-N tunneling program or erase requires high voltage operation. Therefore, the fabrication process is more complicate by including additional process considerations for high-voltage transistors, isolations and junctions, as well as the tunnel oxide and floating-gate. Second, the program and erase operations are not fast (in the range of 10 msec to 100 msec). Third, the endurance of the program-erase cycle is limited to .about.1 million cycles or less due to the degradation of the tunnel oxide by electrons during program or erase.
As a result, the polarization of ferro-electric materials (e.g. PZT) as the non-volatile storage element has been proposed. These materials provide much faster write operations (.about.100 ns), higher cycling endurance (by several orders), and low-voltage operation as described below.
A conventional 1T ferro-electric cell, as shown in U.S. Pat. No. 5,666,305 and as sketched in FIG. 2, is similar to a flash cell except that there is no poly floating-gate needed. The ferro-electric material is fabricated in the multi-layer stack of gate-oxide over the channel. A short review of the basic properties of ferro-electric material for memory application is found in R. E. Jones, "Ferro-Electric Nonvolatile Memories for Embedded Applications", Paper No. 21.4, IEEE Custom Integrated Circuits Conference, p. 431, 1998. The polarization in the ferro-electric layer may have polarities that either reduce or increase the threshold voltage (Vt) of the transistor. Therefore, the polarities of the polarization can be used to represent the digital information of "1" or "0." The polarization can be altered (by the "write" operation) by applying a sufficient electric field with the proper polarity.
The establishment of polarization in the ferro-electric material is due to the separation of polarized atoms in the domains and the growth of polarized domains in the ferro-electric material by applied electric field. It is not related to a physical charge being transported through or to the material. Therefore, the damage of the ferro-electric material by alteration of the polarity polarization is much less than to an oxide by electron tunneling. The endurance of ferro-electric non-volatile cells has been demonstrated to be &gt;10.sup.8 cycles (several orders of magnitude better than tunneling oxide based EEPROM or flash cell). Furthermore, the alteration of polarization is a fast mechanism (in the range of 10 nsec to 100 nsec).
Another prior art non-volatile ferro-electric cell described in R. E. Jones, cited above, is similar to a DRAM. This is shown in FIG. 3 as consisting of one n-MOS transistor connected to a capacitor with a ferro-electric material as the dielectric. The cell can be used as a conventional DRAM cell regardless of the existing polarization in the capacitor. The non-volatile information, stored in the polarization (with either polarity representing "1" or "0") in the capacitor, can be read by sensing the magnitude of charge flowing out of the capacitor when pulsing the plate electrode to a large bias. This read operation of the non-volatile information is a destructive process, since the polarization in each capacitor is forced into the same polarity. Therefore a rewrite operation is required after the read operation.